Got a fast ARM64 self-dev tool, because my homebrewed float80 library behavior on COrtex-M7 looks suspicious. It is also nice that long double on ARM64 linux is 128bit. There is no problem other than M.2/NVME doesn't work at all. Huh? Why?

時間が自由で良いですよぉ〰️

Blue sky... Dangerously hot weather...

I installed a bus terminator SN74ACT1071 into multiplexed address-data bus of W65C816. The bus-hold function works as expected from 2-left to 2-right. 0) output data 2-left) switch to input 1) negate phi0 2-right) bank address output

I got an authentic MSM80C35. I can implement auto detection of CPU type, P8039 or MSM80C39 in my debugger. I had to modify the debugger a bit because the MSM80C35 behaves differently than P8039 after reset and bus cycles of RET/RETR instructions. #MCS48

BionicZ80 implementation has done. It is easy to control 4MHz clock by Teensy 4.1. asciinema.org/a/661752#Z80 Next challenge might be NSC800.

BionicZ80

Z80 can run at 4MHz clock using Teensy 4.1 as the controller. This recording demonstrates Mandelbrot Set drawing using 16-bit integer arithmetics routines written in assembly language. https://gith...

BionicP8051 implementation has done. Xtal freq is about 8MHz. Tuning high speed bit-bang clocking was tough as always. Mandelbrot Set drawing with assembly is quit fast due to 8-bit mul/div instruction. Much better architecture than MCS-48. #MCS51#P8051

I finished tuning P8051 bus cycle. 1.3 MHz ALE (~7.8MHz XTAL). #MCS51

I'm playing with 8051, and now trying to tune with maximu clock 12MHz. A delay from clock edge to control signal is about 50ns which is near the half clock cycle, so that controling by software is quite difficult to tune. Also the phase of external clock differs between HMOS and CMOS.

A noise in 65816 native mode comes from a conflict between read data and bank address on data bus. I can delay a read data at PHI2=H but controll at PHI2=L is tough. Negate PHI2, keep tDHR, switch to input until tBAS, otherwise conflict happens. Try a workaround and running endurance test.