BLUE

EUeprint.bsky.socialOct 4, 2024 8:47am

More Efficient Lattice-based OLE from Circuit-private Linear HE with Polynomial Overhead (Leo de Castro, Duhyeong Kim, Miran Kim, Keewoo Lee, Seonhong Min, Yongsoo Song) ia.cr/2024/1534

Abstract. We present a new and efficient method to obtain circuit privacy for lattice-based linearly homomorphic encryptions (LHE). In particular, our method does not involve noise-flooding with exponetially large errors or iterative bootstrapping. As a direct result, we obtain a semi-honest oblivious linear evaluation (OLE) protocol with the same efficiency, reducing the communication cost of the prior state of the art by 50%. Consequently, the amortized time of our protocol improves the prior work by 33% under 100Mbps network setting. Our semi-honest OLE is the first to achieve both concrete efficiency and asymptotic quasi-optimality. Together with an extension of the recent zero-knowledge proof of plaintext knowledge, our LHE yields actively-secure OLE with 2.7x reduced communication from the prior work. When applied to Overdrive (Eurocrypt ’18), an MPC preprocessing protocol, our method provides 1.4x improvement in communication over the state of the art.

EUeprint.bsky.socialOct 4, 2024 8:47am

Bitwise Garbling Schemes — A Model with $\frac{3}{2}\kappa$-bit Lower Bound of Ciphertexts (Fei Xu, Honggang Hu, Changhong Xu) ia.cr/2024/1532

Abstract. At Eurocrypt 2015, Zahur, Rosulek, and Evans proposed the model of Linear Garbling Schemes. This model proved a 2κ-bit lower bound of ciphertexts for a broad class of garbling schemes. Since then, several methods have been developed that bypass this lower bound, albeit with a notable limitation: Their reliance on specifically correlated input wire labels restricts their applicability across most gates. At Crypto 2021, Rosulek and Roy presented the innovative “three-halves” garbling scheme in which AND gates cost 1.5κ + 5 bits and XOR gates are free. A noteworthy aspect of their scheme is the slicing-and-dicing technique, which is applicable universally to all AND gates when garbling a boolean circuit. Following this revelation, Rosulek and Roy presented several open problems. Our research primarily addresses one of them: “Is 1.5κ bits optimal for garbled AND gates in a more inclusive model than Linear Garbling Schemes?’’

In this paper, we propose the Bitwise Garbling Schemes, a model that seamlessly incorporates the slicing-and-dicing technique. Our key revelation is that 1.5κ bits is indeed optimal for arbitrary garbled AND gates in our model. Since Rosulek and Roy also suggested another problem which questions the necessity of free-XOR, we explore constructions without free-XOR and prove a 2κ-bit lower bound. Therefore, sacrificing compatibility with free-XOR does not lead to a more efficient scheme.

COcianodonnell.bsky.socialOct 4, 2024 8:36am

"Excitation/Inhibition imbalance" is a popular theory for brain disorders eg ASD & schizophrenia. Even a clinical trial for a GABA-B agonist in ASD (clinicaltrials.gov/study/NCT03...).  But I just don't get it.  In this diagram of an E-I circuit, which synapses count as excitatory vs inhibitory?

Simple circuit diagram of excitatory-inhibitory recurrent neural network, with all possible synapse types indicated.

TMtommyreckless.bsky.socialOct 4, 2024 8:27am

When did you do your stand up Graeme? Was it on the Scottish comedy circuit?

schizanon.mastodon.social.ap.brid.gyOct 4, 2024 8:10am

I feel like a #TPM #trustedComputing #encryption #uefi #cryptography #security #infosec

a TPM, a small circuit board with a chip and a TPM 2.0 socket.

THthehalt.bsky.socialOct 4, 2024 8:05am

A metal shutter, buckling on Wesleyan brick, no light, no power. To whom is left this relic of the Methodist Circuit? (41/68, 'White Thorns', 2017)

Ppytorch.krOct 4, 2024 7:44am

AlphaChip: 강화학습(RL) 기반의 칩 배치 생성 방법에 대한 연구 (feat. Google) (by 9bow님) https://d.ptln.kr/5291 #google #ai-chip #reinforcement-learning #tpu #circuit-design #trilium #replace #edge-gnn #markov-decision-process #floorplan #alphachip

AlphaChip: 강화학습(RL) 기반의 칩 배치 생성 방법에 대한 연구 (feat. Google)

들어가며 :pytorch:🇰🇷 지난 9월 말 AlphaChip이라고 이름 붙인, 강화학습 기반의 칩 배치 생성 방법에 대한 짧은 추가 논문(Addendum)이 nature에 공개되었습니다. AlphaChip은 지난 2020년 공개된 강화학습(RL) 기반의 칩 설계 및 배치(Chip Design & Placement) 생성 방법에 대한 연구(A graph placement methodology for fast chip design)를 기반으로 하고 있으며, Google의 TPU 설계에 실제로 적용된 것으로 유명합니다. 이번에 추가된 논문(Addendum)에서는 사전학습을 활용한 효율성 증대를 비롯하여 초기 배치와 벤치마크 등에 대한 내용을 다루고 있습니다. 이러한 추가 논문 이해를 위해 먼저 지난 2020년 공개된 논문 내용을 간략히 다루고, 추가된 내용을 살펴보도록 하겠습니다. AlphaChip의 기반 연구: A graph placement methodology for fast...

CScircuitstatic.bsky.socialOct 4, 2024 7:10am

NEW ALBUM !!! Out Today for #Bandcamp #Friday circuitstatic.bandcamp.com/album/infini...#Samhain #Cinematic #Neo-Pagan#BandcampFriday

Infinity Void, by Circuit Static

13 track album

JWarghzombies.bsky.socialOct 4, 2024 6:17am

Yeah, it's doing the festival circuit trying to drum up interest to get distribution. I hope it does, it's a fun sequel. Utter trash, sure, but a cool idea. And a lot better than the original.

LBbreakintoprogram.bsky.socialOct 4, 2024 6:05am

I’m using Veroboard for my Spectrum project for that authentic 80s vibe. But you don’t have to. There are options like this if you want to interface a circuit with your Spectrum.

Llinker3000.bsky.socialOct 4, 2024 12:50am

Oh, neat! Recreating the original on Veroboard is both awesome and a cool challenge. I know this is not useful for this project, but perhaps for something else later - here's a board I laid out. github.com/linker3000/Z...

GitHub - linker3000/ZX-Spectrum-Breakout-Board: A plug-in PCB for the ZX Spectrum that can be populated with your own project

A plug-in PCB for the ZX Spectrum that can be populated with your own project - linker3000/ZX-Spectrum-Breakout-Board